Switching topics to I/O and game controller support, this week we look briefly at the PIA for Project Ember
The Ember PIA — Initial Design Part 1: Peripheral Interface Adapter
https://skicat.medium.com/21f7f4abb2e8
#verilog
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Boards look great! Starting the slow bring up with just the CPU, RAM, and ROM...and, of course, clock circuit and logic analyzer...
Next, we'll explore the details of the GPU and the initial design of the first simple text mode display!
The Flame GPU — Initial Design Part 2: Tilesheets, Tilemaps, and Graphics Registers
https://medium.com/the-ember-project/the-flame-gpu-initial-design-part-2-tilesheets-tilemaps-and-graphics-registers-8c638a19ec4f
The Ember Console — System Architecture Design: Basic Requirements
https://medium.com/the-ember-project/the-ember-console-system-architecture-design-basic-requirements-97de358a952a
Moving on to the system design, this is an overview of the remaining parts we need to design in order to create a working system capable of playing 80s and 90s-era homebrew video games.
A compelling case for using Bluespec System Verilog: Insights from redesigning a capstone project https://incoresemi.com/a-compelling-case-for-using-bsv-bluespec-system-verilog-in-academia-insights-from-redesigning-a-capstone-project/ @incoresemi #verilog @bluespec
All the equivalent circuit models of neurons written in an #verilog would be a cool project
Every #verilog tool I've tried has a different, unique workaround for specifying an include path that contains a '+' character. So much for universal ".f" filelist file formats.
Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c
[New Blog Post] Comparing Two Verilog CPU Implementations using EBMC https://www.philipzucker.com/td4_ebmc/ #verilog #formal
Hey There Buddo! · Comparing Two Verilog CPU Implementations using EBMCAbout a year ago my friends and I built a 4bit cpu out of a kit from aliexpress. https://www.philipzucker.com/td4-4bit-cpu/ It’s a lot of fun. I also think the system is so simple that is is kind of a nice target for tinkering around with formal methods.
We are Hiring!
FPGA Developer
Location: Remote
Submit your CV: resumes@overturerede.zohorecruitmail.in
Contact: +917428694900
Apply Now: .
https://zurl.co/IeK73
Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.
Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog
I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out 
#GutenMorgen, Ihr lieben Frühwürmchen!
Eine Gruppe Wissenschaftlys zeigte gestern Abend schon reges Interesse an meinem zweiten Poster, das heute dran ist. Nun überlege ich also, das nochmal etwas umzubauen: die Erklärung "Was ist denn so ein #FPGA überhaupt?" kürzen, dafür dann Blockdiagramm, Datenfluss, #Verilog-Quellcode der beiden wesentlichen Algorithmen drauf.
Hmm …
Habt 1 durchdesignten Tag!
Continued thread
Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
https://www.youtube.com/watch?v=wWdvuAQXeS0
![module fizzbuzz #(
parameter MAX_COUNT = 100
)(
input wire clk,
input wire reset,
output reg fizz,
output reg buzz,
output reg num,
output reg [$clog2(MAX_COUNT):0] number
);
reg [$clog2(MAX_COUNT):0] counter;
always @(posedge clk or posedge reset) begin
if (reset) begin
number <= 0;
counter <= 1;
fizz <= 0;
buzz <= 0;
num <= 0;
end else begin
counter <= counter + 1;
number <= counter;
fizz <= counter % 3 == 0;
buzz <= counter % 5 == 0;
num <= counter % 3 > 0 && counter % 5 > 0;
end
end
endmodule](https://files.mastodon.social/media_attachments/files/113/827/942/508/902/697/original/c035353786c98393.png)
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Today's #AdventOfCode part1 was again a surprisingly fast success (anonymous variables in #perl ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (#verilog), and will also have the 10yo learn how to solve it (#python). Thanks a lot to @ericwastl for not ruining Sunday with a 3d falling grid problem!
GIF
Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl
Hackaday · Did You Know YoSys Knows VHDL Too?We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write…