GNU/ #emacs as a full fledged #vhdl #ide, using #guix.

https://git.sr.ht/~csantosb/emacs.vhdl-ide

Ersatz für das Gate-Array in der 1541

Es gibt nur wenige Komponenten im Commodore 1541-Laufwerk, die gerne sterben. Das Gate Array, UC1 oder MOS 325572-01 ist eines davon. Und Ersatz ist nicht billig. Aber man kann sich auch einfach selber eines bauen.

#1541 #32557201 #Array #commodore #CSG #EasyGate1541 #FPGA #Gate #MOS #PCB #PLA #Replacement #Schematic #VC1541 #VHDL #XC95144XL #XC9572XL

https://dirkwouters.de/easygate1541/

Might as well give this a shot.

I want to get out of my current field and do something I can be happy with for a company I can feel good about. I'm currently in the SE US, but want to move back to mid-Atlantic/ North East. Remote is good too.

I have over 10 years of experience of various odd jobs in the embedded electronics space. I'm often moved around as I pick things up quickly and give insight others find valuable.
I've done FPGA verification, FPGA design, software and hardware reverse engineering. I have at least some experience with most standard embedded communication protocols and am very at home in electronics labs. I've recently been self teaching web dev using #Flask. I know #VHDL , #python , a bit rusty on #tcl , #c , and #cpp.
#FediHire #getfedihired

#cocotb, a #freesoftware cosimulation testbench environment for verifying #VHDL and #SystemVerilog #RTL using #Python, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install python-cocotb

This means too that pre-built substitutes are available online .

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c

We are Hiring!
FPGA Developer

Location: Remote

Submit your CV: resumes@overturerede.zohorecruitmail.in

Contact: +917428694900

Apply Now: .
https://zurl.co/IeK73

驗證 VHDL - Hackster.io
➤ 使用 UVVM 簡化 VHDL 測試
✤ https://www.hackster.io/adam-taylor/verifying-vhdl-da9a93
本文介紹使用 GHDL 和 UVVM 進行 VHDL 設計的驗證過程，包括在 Windows 和 Linux 環境中安裝與配置 GHDL，整合至 VS Code，以及如何設置 UVVM 以提升 FPGA 測試的效率與可重用性。
+ 這篇文章提供了詳細而實用的指導，對於想學習 VHDL 驗證的人來說非常有幫助！
+ 感謝作者分享這麼完整的流程，讓我對如何在 FPGA 開發中使用 UVVM 提升效率有了更清晰的瞭解。
#FPGA #VHDL #驗證

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

Would you like to become my new colleague? #fpga #VHDL #work #eda

https://www.finn.no/job/fulltime/ad.html?finnkode=386844647

Commodore 64 PLA chip recreated in VHDL

https://makertube.net/videos/watch/4b79b6af-23b2-46bf-8b2c-4911da8f557f

Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit.
https://sourceforge.net/projects/xschem/

Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl

This #VHDL code is producing low outputs when I'm expecting high. Guess I'll just invert the signal instead of looking into the actual problem. Surely this won't cause problems later and result in 2 hours of debugging. Surely not...

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded

#ghdl (in its #clang variant), a #freesofware #vhdl analyzer, compiler, simulator and synthesizer, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install ghdl-clang

This means too that pre-built substitutes are available online.

Over the months I've put so many hours into trying to get GHDL to work on all Debian architectures, but now I've finally cut my losses and uploaded a new version 4.1.0+dfsg-4 restricted to the architectures that actually work (but hey, amd64 and arm64 are included) to unstable.

There's some serious work that would need to be done to make it portable (and I attempted some of it) and I don't think it's worth it.