We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

\o/

Vive l'opensource,
vive le FPGA libre
vive l'europe ;)

https://blog.yosyshq.com/p/an-open-source-fpga-toolchain-for-a-large-european-space-grade-fpga/

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain.

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.

https://discord.gg/gD3tCpbM

Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl

Just purchased some new FPGA toys... An iCESugar and a pico-ice.

I'd like to finally play around with yosys and nextpnr. Looks like yosys is a bit old on Void, and there isn't a nextpnr package.

I'm half tempted to go through the effort of packaging these for Void Linux so others can benefit.
#FPGA #yosys #icesugar #pico_ice

#Guix channel for #digitalelectronics design, mainly #vhdl and #fpga

https://gitlab.com/csantosb/guix/channel-electronics

So far, with #cocotb, #vunit, #yosys, #osvvm and #ghdl (including its yosys plugin).

Use with:

git clone --depth=1 https://git.sr.ht/~csantosb/guix.channel-electronics
guix install -L ./guix.channel-electronics ghdl-clang

With #guix, this is what it takes to produce a netlist for the 7 series of #xilinx #fpga devices.

> guix install yosys-clang ghdl-clang ghdl-yosys-plugin

> yosys -p 'ghdl --std=08 leds; synth_xilinx -top leds -family xc7 -ise'

It uses only #freesoftware, with #yosys and the #ghdl synthesis module as its backend.

My #tinytapeout 4 submission lives!

A counter doesn't look very impressive, but it has some complexity behind it :) The chip consists of a single NAND and 128 registers. "Instructions" which consist of 2 read addresses and 1 write address are fed to the chip via the IO pins.

The adder is hand written, but for the 7 segment decoder, I ended up writing a very simple #yosys backend

Both the chip and the "circuit" running on it is is written in https://spade-lang.org/

Less than a week to go until out next #yosys user's group!

We'll be hosting a range of FPGA lightning talks & are thrilled to announce the following participants & their projects:

️Pat Deegan's TT ASIC Simulator
️Frans Skarman's Using a raspberry pi camera with an FPGA
️Martín Heredia's EDU-FPGA: teaching digital design with open source FPGA tools
️Sasko Simonovski's FPGA-based Open Source USB security key

Wanna participate in our next #yosys user group lightning talks about your #FPGA project using the open source tools? We'd love to hear from you! Just fill out the linked form.

https://docs.google.com/forms/d/1gKbUfBqs5eMpPQztjnyAxx75a8SGbjkXN-BR2Nn1XF0/viewform?edit_requested=true

From a few years ago when I had to use an intel FPGA. Sure makes me appreciate being able to use #yosys and friends for all my FPGA dev these days

Got slack? I've got slaaaaaack!
#fpga #ulx3s #yosys

Showerthought: can we do coarse grained incremental re-compilation with #yosys

The design I'm working on at the moment consists of 3 major parts: a dram controller with a risc-v core, a camera decoder that writes pixel data into dram, and an HDMI controller that displays the camera feed.

I almost never modify more than one, so why do I need to re-synth and re-pnr the other two? Going from 3 minute rebuilds to 1 minute would be amazing!

Don't miss the next #yosys usergroup tomorrow!

Katharina Ceesay-Seitz & Flavien Solt from ETH Zürich will introduce their tool for Information Flow Tracking

Read more here: https://comsec.ethz.ch/research/hardware-design-security/cellift/

Join us on Thursday, 21st March at 18:00 CET here: https://meet.jit.si/yosys-users-group

Read up on past YUGs: https://blog.yosyshq.com/yug/

And sign up to our newsletter if you want a reminder: https://blog.yosyshq.com/newsletter/